The present invention relates to a chipset with LPC interface, especially to a chipset with LPC interface and data accessing time adapting function.
The conventional ISA (Industry Standard Architecture) interface becomes obsolete and insufficient as the requirement of transmission bandwidth becomes more demanding. The ISA interface has low operation clock rate and high pin counts (such as 60 pins) as compared with other advanced interface. Therefore, the peripheral connected to ISA slot has larger area and small data bandwidth. To overcome this problem, a new interface, namely, LPC (low pin counts) interface is developed. The LPC interface has higher clock rate of 33 MHz and smaller pin counts (below 10 pins). Therefore, the adaptor card and slot for LPC interface have compact size and lower price.
On the other hand, there are still many low-speed peripherals connected to computer through ISA interface. FIG. 1 shows a conventional controller chip to solve this problem. The controller chip 10 comprises an ISA master controller 12 and an LPC master controller 16. The ISA master controller 12 controls a plurality of ISA devices such as a first ISA device 142 to an Mth ISA device 148 through an ISA bus 125. The LPC master controller 16 controls a plurality of LPC devices such as a first LPC device 182 to an Nth LPC device 188 through an LPC bus 165. However, in this scheme, both ISA master controller 12 and LPC master controller 16 are required. The extra pin count imposes difficulty to chip design and motherboard layout.
FIG. 2 shows the block diagram of an improved controller chip 20. The controller chip 20 comprises an LPC master controller 22 controlling a plurality of LPC devices such as a first LPC device 282 to an Nth LPC device 288 through an LPC bus 225. The system further comprises a super I/O chip 24 to control ISA devices with lower clock rate, which include a first ISA device 266 to an Mth ISA device 268. The super I/O chip 24 comprises an LPC slave controller 242 connecting to the LPC master controller 22 through the LPC bus 225. The super I/O chip 24 further comprises a plurality of ISA controlling logic units including a first ISA controlling logic unit 246 to an Mth ISA controlling logic unit 248 in order to control the first ISA device 266 to the Mth ISA device 268, respectively. Every one of the ISA controlling logic units is connected to the LPC slave controller 242 through an LPC/ISA bridge 244. The LPC/ISA bridge 244 is functioned to adapt the signals in LPC format from the LPC master controller 22 into ISA format.
The LPC bus is generally operated at 33 MHz, which is much higher than 8 MHz cock rate of the ISA bus. Therefore, the data accessing time in LPC interface specification such as accessing time for I/O read, I/O write, memory read, memory write, DMA (direct memory access) read/write may be shorter than the data accessing time in ISA interface specification. The cycle numbers of wait state of the signals in LPC format should be prolonged when the signals in LPC format are adapted into ISA format. Therefore, the adapted ISA data has more clock cycles than the original LPC data. However, low-speed peripherals such as printer and disk driver need more clocks for data transmission, it would have transmission problem when the clock cycle number is not sufficient. Moreover, the transmission efficiency is degraded when the cycle number is excessive.
It is an object of the present invention to provide a chipset with LPC interface and data accessing time adapting function, wherein a data accessing time adjuster is provided in the LPC/ISA bridge of the inventive chipset. The data accessing time adjuster adjust accessing time in view of particular ISA or LPC devices.
It is another object of the present invention to provide a chipset with LPC interface and data accessing time adapting function, wherein the data accessing time adjuster comprises a register to record the required time of accessing operation for the ISA or LPC device.
It is still another object of the present invention to provide a chipset with LPC interface and data accessing time adapting function, wherein numbers of wait state cycles is added in the accessing operation to control the accessing time.
It is still another object of the present invention to provide a chipset with LPC interface and data accessing time adapting function, wherein a counter is provided to control the accessing time.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which: